NDLI: Energy efficient ADC design with low voltage operation

Content Provider	IEEE Xplore Digital Library
Author	Matsuzawa, A.
Copyright Year	2011
Description	Author affiliation: Department of Physical Electronics, Tokyo Institute of Technology, S3-27, 2-12-1, O-okayama, Meguro-ku, 152-8552, Japan (Matsuzawa, A.)
Abstract	This paper discusses energy efficient ADC design with low voltage operation. In SAR ADCs, the energy consumption stays constant in the S&H circuit and increases in the comparator with supply voltage, VDD. However, the energy consumed by the logic gates can be reduced using low VDD. Thus, the optimum VDD which minimizes the total energy consumption in SAR ADCs can be found. In flash ADCs, the ENOB is mainly determined by mismatch voltages of the comparators and the energy consumption can be reduced by using lower VDD; however, it also reduces conversion frequency. Thus, we proposed FoM delay product (FD product) that offers the balance between the energy consumption and conversion speed. The optimum VDD that minimizes FD product can be found. A 0.5 V 5-bit 600 MSps flash ADC has been developed and demonstrated the usefulness of reducing VDD to decrease the energy consumption without serious degradation of the performance.
Starting Page	508
Ending Page	511
File Size	1560515
Page Count	4
File Format	PDF
ISBN	9781612841922
ISSN	2162755X
e-ISBN	9781612841939
e-ISBN	9781612841915
DOI	10.1109/ASICON.2011.6157233
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DVD
Content Type	Text
Resource Type	Article

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