NDLI: Design and verification of an application-specific PLD using VHDL and SystemVerilog

Content Provider	IEEE Xplore Digital Library
Author	Jae-Jin Lee Young-Jin Oh Gi-Yong Song
Copyright Year	2011
Description	Author affiliation: Electrionics and Telecommunications Reaserch Institute, 218 Gajeongno,Yuseong-gu, Deajeon, Korea (Jae-Jin Lee) \|\| School of Electronics engineering College of Electrical and Computer Engineering, Chungbuk National University Cheongju, Korea (Young-Jin Oh; Gi-Yong Song)
Abstract	This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cell contains another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the routing requirement in the PLD to local interconnections between Logic Units and to global interconnections between Logic Modules. The maximum clock cycle is limited only by one AND gate and one full adder. Operations of convolution and FIR filter implemented on the proposed PLD are checked using a SystemVerilog-coded verification platform.
Starting Page	159
Ending Page	162
File Size	1156942
Page Count	4
File Format	PDF
ISBN	9781612841922
ISSN	2162755X
e-ISBN	9781612841939
e-ISBN	9781612841915
DOI	10.1109/ASICON.2011.6157146
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Generators Arrays Clocks
Content Type	Text
Resource Type	Article

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