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| Content Provider | ACM Digital Library |
|---|---|
| Author | Xie, Yuan Zhang, Tao Wang, Tao Sun, Guangyu Xu, Cong Chen, Ke |
| Abstract | DRAM memory is a major contributor for the total power consumption in modern computing systems. Consequently, power reduction for DRAM memory is critical to improve system-level power efficiency. Fine-grained DRAM architecture [1, 2] has been proposed to reduce the activation/ precharge power. However, those prior work either incurs significant performance degradation or introduces large area overhead. In this paper, we propose a novel memory architecture Half-DRAM, in which the DRAM array is reorganized to enable only half of a row being activated. The half-row activation can effectively reduce activation power and meanwhile sustain the full bandwidth one bank can provide. In addition, the half-row activation in Half-DRAM relaxes the power constraint in DRAM, and opens up opportunities for further performance gain. Furthermore, two half-row accesses can be issued in parallel by integrating the sub-array level parallelism to improve the memory level parallelism. The experimental results show that Half-DRAM can achieve both significant performance improvement and power reduction, with negligible design overhead |
| Starting Page | 349 |
| Ending Page | 360 |
| Page Count | 12 |
| File Format | |
| ISSN | 01635964 |
| DOI | 10.1145/2678373.2665724 |
| Journal | ACM SIGARCH Computer Architecture News (CARN) |
| Volume Number | 42 |
| Issue Number | 3 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1981-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Content Type | Text |
| Resource Type | Article |
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