NDLI: An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

Content Provider	ACM Digital Library
Author	Sampson, Jack Swaminathan, Karthik Liu, Huichu Narayanan, Vijaykrishnan
Abstract	For any given application, there is an optimal throughput point in the space of per-processor performance and the number of such processors given to that application. However, due to thermal, yield, and other constraints, not all of these optimal points can plausibly be constructed with a given technology. In this paper, we look at how emerging steep slope devices, 3D circuit integration, and trends in process technology scaling will combine to shift the boundaries of both attainable performance, and the optimal set of technologies to employ to achieve it. We propose a heterogeneous-technology 3D architecture capable of operating efficiently at an expanded number of points in this larger design space and devise a heterogeneity and thermal aware scheduling algorithm to exploit its potential. Our heterogeneous mapping techniques are capable of producing speedups ranging from 17% for a high end server workloads running at around 90°C to over 160% for embedded systems running below 60°C
Starting Page	241
Ending Page	252
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2678373.2665709
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	42
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs