NDLI: Increasing off-chip bandwidth in multi-core processors with switchable pins

Content Provider	ACM Digital Library
Author	Chen, Shaoming Hu, Yue Ardonne, Jesse Zhang, Ying Peng, Lu Irving, Samuel Srivastava, Ashok
Abstract	Off-chip memory bandwidth has been considered as one of the major limiting factors to processor performance, especially for multi-cores and many-cores. Conventional processor design allocates a large portion of off-chip pins to deliver power, leaving a small number of pins for processor signal communication. We observed that the processor requires much less power than that can be supplied during memory intensive stages. This is due to the fact that the frequencies of processor cores waiting for data to be fetched from off-chip memories can be scaled down in order to save power without degrading performance. In this work, motivated by this observation, we propose a dynamic pin switch technique to alleviate the bandwidth limitation issue. The technique is introduced to dynamically exploit the surplus pins for power delivery in the memory intensive phases and uses them to provide extra bandwidth for the program executions, thus significantly boosting the performance
Starting Page	385
Ending Page	396
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2678373.2665730
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	42
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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Increasing off-chip bandwidth in multi-core processors with switchable pins