NDLI: Reducing access latency of MLC PCMs through line striping

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Unifying on-chip and inter-node switching within the Anton 2 network

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The Direct-to-Data (D2D) cache

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A reconfigurable fabric for accelerating large-scale datacenter services

Enabling preemptive multiprogramming on GPUs

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

Reducing access latency of MLC PCMs through line striping

Increasing off-chip bandwidth in multi-core processors with switchable pins

The dirty-block index

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Real-world design and evaluation of compiler-managed GPU redundant multithreading

Harnessing ISA diversity

Going vertical in memory management

Replay debugging

Improving the energy efficiency of big cores

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Volume 42, Issue 1, March 2014

Reducing access latency of MLC PCMs through line striping

Content Provider	ACM Digital Library
Author	Arjomand, Mohammad Hoseinzadeh, Morteza Sarbazi-Azad, Hamid
Abstract	Although phase change memory with multi-bit storage capability (known as MLC PCM) offers a good combination of high bit-density and non-volatility, its performance is severely impacted by the increased read/write latency. Regarding read operation, access latency increases almost linearly with respect to cell density (the number of bits stored in a cell). Since reads are latency critical, they can seriously impact system performance. This paper alleviates the problem of slow reads in the MLC PCM by exploiting a fundamental property of MLC devices: the Most-Significant Bit (MSB) of MLC cells can be read as fast as SLC cells, while reading the Least-Significant Bits (LSBs) is slower. We propose Striped PCM (SPCM), a memory architecture that leverages this property to keep MLC read latency in the order of SLC's. In order to avoid extra writes onto memory cells as a result of striping memory lines, the proposed design uses a pairing write queue to synchronize write-back requests associated with blocks that are paired in striping mode. Our evaluation shows that our design significantly improves the average memory access latency by more than 30% and IPC by up to 25% (10%, on average), with a slight overhead in memory energy (0.7%) in a 4-core CMP model running memory-intensive benchmarks
Starting Page	277
Ending Page	288
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2678373.2665713
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	42
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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