NDLI: Memory persistency

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Volume 42, Issue 5, December 2014

Volume 42, Issue 4, Setember 2014

Volume 42, Issue 3, June 2014

Unifying on-chip and inter-node switching within the Anton 2 network

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The Direct-to-Data (D2D) cache

Fine-grain task aggregation and coordination on GPUs

Efficient digital neurons for large scale cortical architectures

Memory persistency

Towards energy proportionality for large-scale latency-critical workloads

Row-buffer decoupling

Architecture implications of pads as a scarce resource

The CHERI capability model

General-purpose code acceleration with limited-precision analog computation

A reconfigurable fabric for accelerating large-scale datacenter services

Enabling preemptive multiprogramming on GPUs

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

Reducing access latency of MLC PCMs through line striping

Increasing off-chip bandwidth in multi-core processors with switchable pins

The dirty-block index

Single-graph multiple flows

Optimizing virtual machine consolidation performance on NUMA server architecture for cloud workloads

Flipping bits in memory without accessing them

A low power and reliable charge pump design for phase change memories

Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization

Real-world design and evaluation of compiler-managed GPU redundant multithreading

Harnessing ISA diversity

Going vertical in memory management

Replay debugging

Improving the energy efficiency of big cores

Volume 42, Issue 2, May 2014

Volume 42, Issue 1, March 2014

Memory persistency

Content Provider	ACM Digital Library
Author	Pelley, Steven Wenisch, Thomas F. Chen, Peter M.
Abstract	Emerging nonvolatile memory technologies (NVRAM) promise the performance of DRAM with the persistence of disk. However, constraining NVRAM write order, necessary to ensure recovery correctness, limits NVRAM write concurrency and degrades throughput. We require new memory interfaces to minimally describe write constraints and allow high performance and high concurrency data structures. These goals strongly resemble memory consistency. Whereas memory consistency concerns the order that memory operations are observed between numerous processors, persistent memory systems must constrain the order that writes occur with respect to failure. We introduce memory persistency, a new approach to designing persistent memory interfaces, building on memory consistency. Similar to memory consistency, memory persistency models may be relaxed to improve performance. We describe the design space of memory persistency and desirable features that such a memory system requires. Finally, we introduce several memory persistency models and evaluate their ability to expose NVRAM write concurrency using two implementations of a persistent queue. Our results show that relaxed persistency models accelerate system throughput 30-fold by reducing NVRAM write constraints
Starting Page	265
Ending Page	276
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2678373.2665712
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	42
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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