NDLI: Real-world design and evaluation of compiler-managed GPU redundant multithreading

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Volume 42, Issue 5, December 2014

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Unifying on-chip and inter-node switching within the Anton 2 network

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The Direct-to-Data (D2D) cache

Fine-grain task aggregation and coordination on GPUs

Efficient digital neurons for large scale cortical architectures

Memory persistency

Towards energy proportionality for large-scale latency-critical workloads

Row-buffer decoupling

Architecture implications of pads as a scarce resource

The CHERI capability model

General-purpose code acceleration with limited-precision analog computation

A reconfigurable fabric for accelerating large-scale datacenter services

Enabling preemptive multiprogramming on GPUs

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

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Increasing off-chip bandwidth in multi-core processors with switchable pins

The dirty-block index

Single-graph multiple flows

Optimizing virtual machine consolidation performance on NUMA server architecture for cloud workloads

Flipping bits in memory without accessing them

A low power and reliable charge pump design for phase change memories

Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization

Real-world design and evaluation of compiler-managed GPU redundant multithreading

Harnessing ISA diversity

Going vertical in memory management

Replay debugging

Improving the energy efficiency of big cores

Volume 42, Issue 2, May 2014

Volume 42, Issue 1, March 2014

Real-world design and evaluation of compiler-managed GPU redundant multithreading

Content Provider	ACM Digital Library
Author	Wadden, Jack Sridharan, Vilas Lyashevsky, Alexander Skadron, Kevin Gurumurthi, Sudhanva
Abstract	Reliability for general purpose processing on the GPU (GPGPU) is becoming a weak link in the construction of reliable supercomputer systems. Because hardware protection is expensive to develop, requires dedicated on-chip resources, and is not portable across different architectures, the efficiency of software solutions such as redundant multithreading (RMT) must be explored. This paper presents a real-world design and evaluation of automatic software RMT on GPU hardware. We first describe a compiler pass that automatically converts GPGPU kernels into redundantly threaded versions. We then perform detailed power and performance evaluations of three RMT algorithms, each of which provides fault coverage to a set of structures in the GPU. Using real hardware, we show that compilermanaged software RMT has highly variable costs. We further analyze the individual costs of redundant work scheduling, redundant computation, and inter-thread communication, showing that no single component in general is responsible for high overheads across all applications; instead, certain workload properties tend to cause RMT to perform well or poorly. Finally, we demonstrate the benefit of architectural support for RMT with a specific example of fast, register-level thread communication
Starting Page	73
Ending Page	84
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2678373.2665686
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	42
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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