NDLI: The Direct-to-Data (D2D) cache:navigating the cache hierarchy with a single lookup

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Volume 42, Issue 5, December 2014

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Volume 42, Issue 3, June 2014

Unifying on-chip and inter-node switching within the Anton 2 network

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The Direct-to-Data (D2D) cache

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Architecture implications of pads as a scarce resource

The CHERI capability model

General-purpose code acceleration with limited-precision analog computation

A reconfigurable fabric for accelerating large-scale datacenter services

Enabling preemptive multiprogramming on GPUs

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs

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Real-world design and evaluation of compiler-managed GPU redundant multithreading

Harnessing ISA diversity

Going vertical in memory management

Replay debugging

Improving the energy efficiency of big cores

Volume 42, Issue 2, May 2014

Volume 42, Issue 1, March 2014

The Direct-to-Data (D2D) cache:navigating the cache hierarchy with a single lookup

Content Provider	ACM Digital Library
Author	Black-Schaffer, David Hagersten, Erik Sembrant, Andreas
Abstract	Modern processors optimize for cache energy and performance by employing multiple levels of caching that address bandwidth, low-latency and high-capacity. A request typically traverses the cache hierarchy, level by level, until the data is found, thereby wasting time and energy in each level. In this paper, we present the Direct-to-Data (D2D) cache that locates data across the entire cache hierarchy with a single lookup. To navigate the cache hierarchy, D2D extends the TLB with per cache-line location information that indicates in which cache and way the cache line is located. This allows the D2D cache to: 1) skip levels in the hierarchy (by accessing the right cache level directly), 2) eliminate extra data array reads (by reading the right way directly), 3) avoid tag comparisons (by eliminating the tag arrays), and 4) go directly to DRAM on cache misses (by checking the TLB). This reduces the L2 latency by 40% and saves 5-17% of the total cache hierarchy energ D2D's lower L2 latency directly improves L2 sensitive applications' performance by 5-14%. More significantly, we can take advantage of the L2 latency reduction to optimize other parts of the micro-architecture. For example, we can reduce the ROB size for the L2 bound applications by 25%, or we can reduce the L1 cache size, delivering an overall 21% energy savings across all benchmarks, without hurting performance.
Starting Page	133
Ending Page	144
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2678373.2665694
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	42
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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