NDLI: Efficient digital neurons for large scale cortical architectures

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Unifying on-chip and inter-node switching within the Anton 2 network

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The Direct-to-Data (D2D) cache

Fine-grain task aggregation and coordination on GPUs

Efficient digital neurons for large scale cortical architectures

Memory persistency

Towards energy proportionality for large-scale latency-critical workloads

Row-buffer decoupling

Architecture implications of pads as a scarce resource

The CHERI capability model

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Real-world design and evaluation of compiler-managed GPU redundant multithreading

Harnessing ISA diversity

Going vertical in memory management

Replay debugging

Improving the energy efficiency of big cores

Volume 42, Issue 2, May 2014

Volume 42, Issue 1, March 2014

Efficient digital neurons for large scale cortical architectures

Content Provider	ACM Digital Library
Author	Smith, James E.
Abstract	Digital neurons are implemented with the goal of sup-porting research and development of architectures which implement the computational paradigm of the neocortex. Four spiking digital neurons are implemented at the register transfer level in a manner that permits side-by-side comparisons. Two of the neurons contain two stages of ex-ponential decay, one for synapse conductances and one for membrane potential. The other two neurons contain only one stage of exponential decay for membrane potential. The two stage neurons respond to an input spike with a change in membrane potential that has a non-infinite lead-ing edge slope; the one stage neurons exhibit a change in membrane potential with an abrupt, infinite leading edge slope. This leads to a behavioral difference when a number of input spikes occur in very close time proximity. However, the one stage neurons are as much as a factor of ten more energy efficient than the two stage neurons, as measured by the number of dynamic add-equivalent operations A new two stage neuron is proposed. This neuron reduc-es the number of decay components and implements decays in both stages via piece-wise linear approximation. Togeth-er, these simplifications yield two stage neuron behavior with energy efficiency that is only about a factor of two worse than the simplest one stage neuron.
Starting Page	229
Ending Page	240
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/2678373.2665707
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	42
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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