NDLI: Power-efficient Instruction Encoding Optimization for Embedded Processors

Content Provider	IEEE Xplore Digital Library
Author	Chattopadhyay, A. Zhang, D. Kammler, D. Witte, E.M. Leupers, R. Ascheid, G. Meyr, H.
Copyright Year	2007
Description	Author affiliation: Aachen Univ. of Technol. (Chattopadhyay, A.; Zhang, D.; Kammler, D.; Witte, E.M.; Leupers, R.; Ascheid, G.; Meyr, H.)
Abstract	The increasing complexity of applications with shortening time-to-market window created a strong research interest towards high-performance and flexible processors. A huge application domain, chiefly consisting of wireless and handheld devices, strongly requires this class of processors to be power-efficient, too. Within this domain, a demanding problem is to determine the instruction encoding of the processor for achieving minimum power consumption in the instruction bus and in the instruction memory. In this paper, a framework for determining power-efficient instruction encoding is presented. The authors have integrated existing and novel techniques in this framework and have proposed novel heuristic approaches. The framework accepts an existing processor instruction-set and a group of applications. The output, which is an optimized instruction encoding under the constraints of a well-defined cost model, minimizes the power consumption of the instruction bus and the instruction memory. This results in strong reduction of the overall power consumption. Case studies with commercial embedded processors show the effectiveness of this framework
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	595
Ending Page	600
File Size	287528
Page Count	6
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Energy consumption Process design Capacitance Power distribution Random access memory Application specific processors Read only memory Power system modeling Hardware
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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