NDLI: Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations

Content Provider	IEEE Xplore Digital Library
Author	Vrudhula, S. Bhardwaj, S.
Copyright Year	2007
Description	Author affiliation: CSE Dept., Arizona State Univ., Tempe, AZ (Vrudhula, S.; Bhardwaj, S.)
Abstract	The lack of process uniformity in the semiconductor manufacturing has caused variability to become the primary cause of concern for nanometer scale CMOS design. The variations are caused by either global effects such as mask imperfections and lens aberration, or local effects such as layout pattern variations. These variations result in a significant amount of spread in the performance as well as leakage of the manufactured circuits. The effect of variations on circuit leakage current is much more pronounced compared to their effect on the delay. The variations can cause up to 30% variations in the circuit delay and up to 20X variations in the leakage current. Due to this, a large number of chips with significantly large leakage have to be discarded, thus resulting in a considerable yield loss. The microelectronics industry is now facing one of the most important and difficult challenges - the loss of predictability in the functional correctness and performance of nanometer scale integrated circuits. For technology to continue to advance along Moore's curve, it has become imperative to develop techniques to both predict and to optimize the performance of ICs in the presence of process variations. The proposed full day tutorial will be a comprehensive look at the state-of-art techniques for (1) accurately predicting the performance and power in the presence of both inter-die and intra-die process variations, accounting for spatial correlations, and (2) optimizing the power and/or performance in the presence of process variations. The tutorial will cover four main topics: 1. Introduction to process variations: sources and their impact 2. Statistical models for gates and interconnect 3. Statistical static timing analysis and total leakage analysis 4. Performance and power optimization in the presence of process variations.
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	9
Ending Page	9
File Size	177333
Page Count	1
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.170
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in