NDLI: MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Rajesh Kumar, T.S. Ravikumar, C.P. Govindarajan, R.
Copyright Year	2007
Description	Author affiliation: Texas Instruments India Ltd., Bangalore (Rajesh Kumar, T.S.; Ravikumar, C.P.)
Abstract	Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	527
Ending Page	533
File Size	898954
Page Count	7
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.102
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Memory architecture Embedded system Videos System-on-a-chip Costs Energy consumption Time to market Genetic algorithms Heuristic algorithms Application specific integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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