NDLI: Tutorial T3: Low Power Design Techniques for Nanometer Design Processes

Content Provider	IEEE Xplore Digital Library
Author	Chattopadhyay, S.
Copyright Year	2007
Description	Author affiliation: Intel Corp., Santa Clara, CA (Chattopadhyay, S.)
Abstract	Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs. In this tutorial we present the importance of low power microprocessor/SOC design from the high level microarchitectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely faced by designers today. Embedded microprocessor/SOC designs are particularly dictated by standby and max/thermal design power and battery life constraints and not performance/frequency alone. Designing with the power envelope is a standard challenge even for the high end server platforms. Performance/watt or MlPS/watt is the design metric of today that we focus on. We cover the main components of leakage power and how does the transistor design determines whether the extreme stringent battery life requirements determined by standby and average power are met. A short discussion of different process variants for various types of applications will also be discussed followed by an introduction of shadow latches and state retention techniques used by microprocessors and DSPs of today. Tradeoff between amount of state retained and the exit latency of the processor from deep sleep/standby states will be discussed. We also cover all areas of focus for low power optimization and design: active power reduction techniques, various leakage power reduction techniques, different types of power optimization techniques from clock gating, clock tree optimization, state assignment for lower power during synthesis, long channel device insertion, multi Vt designs, gate sizing and power optimization based on positive slack in timing to name a few. We also cover the various low power friendly circuit design families as well as various techniques to reduce active power like dynamic voltage scaling, thermal throttling, sleep transistor based shutdown for various blocks like the memory hierarchy. Last but not the least we cover the whole suite of EDA tools geared towards low power estimation and optimization from the ESL domain to layout optimization for low power.
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	5
Ending Page	5
File Size	155204
Page Count	1
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.167
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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