NDLI: Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST

Content Provider	IEEE Xplore Digital Library
Author	Suresh Kumar Devanathan Bushnell, M.L.
Copyright Year	2007
Description	Author affiliation: Dept. of ECE, Rutgers Univ., Piscataway, NJ (Suresh Kumar Devanathan; Bushnell, M.L.)
Abstract	We propose a sequential built-in self-test (BIST) hardware pattern generator using Haar wavelets, linear feedback shift registers (LFSRs), modulation, correlation and biasing hardware that produces higher fault efficiencies (FEs) than existing sequential BIST methods. We generate random bit sequences for primary inputs (PIs), which are modulated by Haar wavelets. Our correlator may substitute a highly-correlated PI bit stream for the actual bit stream for this PI. Finally, the bit stream is biased toward a particular probability of generating a 1 input before being fed to the PI. Results on ISCAS '89 benchmarks show that this BIST method produces 96.77% FE for circuits without re-settable flip-flops, and 99.41% (upper-bound) FE, for those with resettable flip-flops. Upadhyayula and Bushnell (2002) only attained 81.4% FE. Our method is implemented in hardware as opposed to Giani et al. (2001) who have system-on-a-chip (SoC) implementations that require an on-board microprocessor and cannot perform at-speed test. Our hardware overhead is 9.01%, much less than Giani et al.'s method. Compared to Pomeranz and Reddy's work (Pomeranz and Reddy, 1998), we achieved 95.69% FE, compared with 95.01% for them, and on the circuits where they presented results, we have 66.3% hardware overhead versus 234-1% for them
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	485
Ending Page	491
File Size	284909
Page Count	7
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.155
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Test pattern generators Built-in self-test Hardware Iron Flip-flops System-on-a-chip Linear feedback shift registers Circuit faults Correlators Microprocessors
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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