NDLI: Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses

Content Provider	IEEE Xplore Digital Library
Author	Sharath Jayaprakash Mahapatra, N.R.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI (Sharath Jayaprakash; Mahapatra, N.R.)
Abstract	Dynamic bus power dissipation, especially for long global signal buses, is becoming increasingly important with technology scaling due to several reasons: more pronounced interwire coupling effects, higher frequencies, greater traffic demands arising from higher levels of integration (e.g., as seen in system-on-chip and multi-core designs), and power density concerns, among others. While low-power dynamic bus encoding schemes, such as bus invert (BI) and odd-even bus invert (OEBI), have been proposed to reduce bus switching activities, they are not effective for wide microprocessor buses carrying correlated traffic found in typical workloads like SPEC CPU2000 benchmarks. To address this, we propose a partitioned hybrid bus encoding technique in which the bus is partitioned optimally and the most energy-efficient dynamic encoding scheme- we consider bus invert (BI), odd/even bus invert (OEBI), and not encoding as the possible options, but any other collection of schemes can be considered-is independently applied to each partition depending upon traffic value characteristics to minimize total bus (wire self and interwire coupling) dynamic energy. While BI and OEBI provide average energy reductions of only 5.27%/1.58% and 0.98%/1.97% for data/instruction buses, respectively, for SPEC CPU2k benchmarks, our hybrid encoding technique yields average energy savings of 22.07%/27.40% for the same traffic and buses-these results take into account the energy consumed by control lines, too
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	127
Ending Page	134
File Size	247051
Page Count	8
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.126
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Energy dissipation Microprocessors Bismuth Power dissipation Frequency System-on-a-chip Signal design Energy efficiency Wire
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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