NDLI: Zero Cost Test Point Insertion Technique for Structured ASICs

Content Provider	IEEE Xplore Digital Library
Author	Sethuram, R. Seongmoon Wang Chakradhar, S.T. Bushnell, M.L.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ (Sethuram, R.)
Abstract	We show different ways in which unused multiplexers (MUXes) and scan flip-flops (flops) in a structured application specific integrated chip (SA) design can be re-configured to insert test points to drastically reduce test volume and test generation time. We convert unused hardware in SAs into: (a) conventional control points, (b) complete test points, (c) pseudo-control points or (d) inversion test points. Since only unused hardware is used, the proposed test point insertion (TPI) technique does not entail any extra hardware overhead. Test points are inserted using timing information, so they do not degrade performance. We also present novel gain functions that quantify the reduction in test volume and automatic test pattern generation (ATPG) time due to TPI and are used as heuristics to guide the selection of signal lines for inserting test points. Experimental results clearly demonstrate the effectiveness and scalability of the proposed technique. Using very little unused hardware and TPI run time, we reduced ATPG time by up to 63.1 % and test data volume by up to 64.5% while also achieving a near 100% fault efficiency for very large industrial designs
Sponsorship	VLSI Soc. of India IEEE CAS Soc. IEEE ED Soc. ACM IEEE SSC Soc
Starting Page	357
Ending Page	363
File Size	229768
Page Count	7
File Format	PDF
ISBN	0769527620
ISSN	10639667
DOI	10.1109/VLSID.2007.181
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Hardware Automatic test pattern generation National electric code Automatic testing Silicon Field programmable gate arrays Clocks Design for testability Design engineering
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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