NDLI: A junction leakage mechanism and its effects on advance SRAM failure

Content Provider	IEEE Xplore Digital Library
Author	Maji, D. Liao, P.J. Lee, Y.-H. Shih, J.R. Chen, S.C. Gao, S.H. Lee, J.H. Wu, K.
Copyright Year	2013
Description	Author affiliation: Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan (Maji, D.; Liao, P.J.; Lee, Y.-H.; Shih, J.R.; Chen, S.C.; Gao, S.H.; Lee, J.H.; Wu, K.)
Abstract	Junction leakage is becoming an important reliability concern as shallow trench isolation (STI) continues to scale down. This junction leakage has to be considered to improve SRAM Vccmin degradation. The major index of junction leakage in SRAM cell is found to be off-state leakage current as the leakage phenomenon externally manifests as a current flow from butted contact (BCT) to lower pull down (LPD) transistor gate. Isolation test patterns $(P^{+}/N-well$ to P-Well) with well photo misalignments are designed to verify Si/STI interface damage effect on junction leakage. Process experiment with PW misalignment shows isolation leakage current $(P^{+}$ to PW) increase after electrical stress. However, this type of leakage due to PW misalignment shows weak temperature and voltage dependence, indicating that the trap-assisted carrier hopping at STI $Si/SiO_{2}$ interface and the PW misalignment are paramount of SRAM junction reliability. Using TCAD simulation, we have verified that carriers transport through the Si/STI interface traps along with poor PW misalignment is the root causes of the junction leakage current increase. HSPICE simulation results show that junction leakage worsen SRAM cell stability by degrading SRAM read margin (SNM) and may eventually lead to cell failure.
Sponsorship	IEEE Electron Devices Soc.
File Size	618309
File Format	PDF
ISBN	9781479901128
ISSN	19381891
e-ISBN	9781479901135
e-ISBN	9781479901111
DOI	10.1109/IRPS.2013.6531994
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Junctions Leakage currents Silicon Random access memory Stress Reliability Degradation read margin (SNM) junction leakage PW misalignment isolation leakage current
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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