NDLI: Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction

Content Provider	IEEE Xplore Digital Library
Author	Velamala, J.B. Sutaria, K.B. Shimuzu, H. Awano, H. Sato, T. Wirth, G. Yu Cao
Copyright Year	2013
Description	Author affiliation: Sch. of Inf., Kyoto Univ., Kyoto, Japan (Shimuzu, H.; Awano, H.; Sato, T.) \|\| Inst. de Inf., UFRGS, Porto Alegre, Brazil (Wirth, G.) \|\| Sch. of ECEE, Arizona State Univ., Tempe, AZ, USA (Velamala, J.B.; Sutaria, K.B.; Yu Cao)
Abstract	Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete $V_{th}$ shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where $V_{dd}$ is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging; (3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage.
Sponsorship	IEEE Electron Devices Soc.
File Size	516562
File Format	PDF
ISBN	9781479901128
ISSN	19381891
e-ISBN	9781479901135
e-ISBN	9781479901111
DOI	10.1109/IRPS.2013.6532063
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Aging Stress Data models Predictive models Degradation Integrated circuit modeling Charge carrier processes DVS Trapping/de-trapping statistical variations compact modeling negative bias temperature instability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Compact Modeling of Statistical BTI Under Trapping/Detrapping

BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation

Physics matters: Statistical aging prediction under trapping/detrapping

Aging Statistics Based on Trapping/Detrapping: Compact Modeling and Silicon Validation

Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction

Impact of temporal transistor variations on circuit reliability

Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging

Understanding the impact of transistor-level BTI variability

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction

Similar Documents

Compact Modeling of Statistical BTI Under Trapping/Detrapping

BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation

Physics matters: Statistical aging prediction under trapping/detrapping

Aging Statistics Based on Trapping/Detrapping: Compact Modeling and Silicon Validation

Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction

Impact of temporal transistor variations on circuit reliability

Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging

Understanding the impact of transistor-level BTI variability

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction