NDLI: Circuit-dependent F, Power and Process optimization to improve product Reliability, Availability and Serviceability

Content Provider	IEEE Xplore Digital Library
Author	Nsame, P. Nadkarni, R. Klazynski, J.N. Bickford, J. Sumner, K. Susso, B. Kumar, R. Bazan, G. Polson, A. Radaker, R.
Copyright Year	2013
Description	Author affiliation: Syst. & Technol. Group, IBM Corp., Essex Junction, USA (Nsame, P.; Nadkarni, R.; Klazynski, J.N.; Bickford, J.; Sumner, K.; Susso, B.; Kumar, R.; Bazan, G.; Polson, A.) \|\| LSI Corp., USA (Radaker, R.)
Abstract	A fully functional PowerPC476FP SoC communication processor with 4MB eDRAM System Cache achieving 2GHz/Core, in a 4 × 2.5DMIPS/Core/MHz configuration is qualified using physics-of-aging models in a 45nm SOI CMOS technology node including a logic and deep-trench (DT) eDRAM optimized semiconductor process. A novel circuit-depend F<;sub>MAX<;/sub>, Power, and Process optimization methodology that resolves technology reliability limitations (including Stress Migration, EM, BTI, HCI, TDDB, Defects, Package) without product burn-in, while delivering a 9.26% improvement per bin in energy-efficiency across 16 bins and up to 43.9% reduction in failure rate compare to equivalent circuits without the novel optimization methodology is described. Measured results show functional operation with a voltage range of 0.75V to 1.125V, a temperature range of -40C to 125C, speed of 1.8+ GHz at 0.96V, 110C and 90-100% yield performance, for a product lifetime specification of 88KPOH & 2750 ON/OFF cycles. These results demonstrate the highest reliability-aware functional performance reported to date with a 45nm nominal process at 0.9V for a 32-bit Quad-Core communication processor with asymmetric and scalable architecture while achieving the highest reported enterprise-level energy efficiency compare to Quad-Core communication processors in the same class. The technical contributions in this work enables a growing industry trend towards multi-radio ultra-compact stackable base stations designed to drastically reduce the entry price level per base station, enhance scalability and up-gradeability, significantly lower power consumption and enhance flexibility.
Sponsorship	IEEE Electron Devices Soc.
File Size	930338
File Format	PDF
ISBN	9781479901128
ISSN	19381891
e-ISBN	9781479901135
e-ISBN	9781479901111
DOI	10.1109/IRPS.2013.6531997
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit reliability Optimization Error correction codes Reliability engineering Availability Integrated circuit modeling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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