NDLI: Single bit-line 7T SRAM cell for low power and high SNM

Content Provider	IEEE Xplore Digital Library
Author	Madiwalar, B. Kariyappa, B.S.
Copyright Year	2013
Description	Author affiliation: VLSI Design & Embedded Syst., RVCE Bengaluru, Bangalore, India (Madiwalar, B.) \|\| Dept. of ECE, RVCE Bengaluru, Bangalore, India (Kariyappa, B.S.)
Abstract	Memories are integral parts of most of the digital devices and hence reducing power consumption of memory is very important in improving the system performance, efficiency and stability. Most of the embedded and portable devices use SRAM cells because of their ease of use as well as low standby leakage. Standard CMOS 6T SRAM cell uses two bit-lines and a word line for both read and write operations. This 6T SRAM cell consumes more power and shows poor stability at small feature sizes with low power supply. During read operation, the stability drastically decreases due to the voltage division between the access and driver transistors. In this paper new 7T SRAM cell is proposed, which uses single bit-line for both read and write operations. Power consumption is reduced because of single bit line usage and read stability is very high compared to conventional 6T SRAM cell. Proposed cell also provides high static noise margins (SNMs). The proposed 7T SRAM cell is compared with conventional 6T SRAM cell in terms of power consumed, delay and SNMs. The Proposed 7T SRAM cell consumes 22.03% less power for write `0' operation, 17.33% less power for write `1' operation, 17.52% less power for read `0' operation and 21.36% less power for read `1' operation compared to conventional 6T SRAM cell. The proposed cell has 2.64 times SNM in read state; 1.082 times SNM in hold state and 1.064 times SNM in write 0 state compared to conventional 6T SRAM cell. Schematics are drawn using virtuoso ADE of Cadence, and all simulations are carried out using Cadence Spectre Analyzer with 90nm Technology library at 1.8V VDD.
Sponsorship	IEEE Kerala Sect.
Starting Page	223
Ending Page	228
File Size	435827
Page Count	6
File Format	PDF
ISBN	9781467350891
e-ISBN	9781467350907
DOI	10.1109/iMac4s.2013.6526412
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-22
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SNM (Static Noise Margin) WNM (Write Noise Margin) Noise SRAM (Static Random Access Memory) Discharges (electric) Stability analysis Low power Wireless sensor networks Single bit line RNM (Read Noise Margin) Read stable HSNM (Hold State Noise Margin) SRAM cells Transistors 7T-SRAM cell
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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