NDLI: The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Content Provider	IEEE Xplore Digital Library
Author	Raghavan, N. Padovani, A. Wu, X. Shubhakar, K. Bosman, M. Larcher, L. Pey, K.L.
Copyright Year	2013
Description	Author affiliation: Sch. of EEE, Nanyang Technol. Univ. (NTU), Singapore, Singapore (Raghavan, N.) \|\| Singapore Univ. of Technol. & Design (SUTD), Singapore, Singapore (Wu, X.; Shubhakar, K.; Pey, K.L.) \|\| Inst. of Mater. Res. & Eng. (IMRE), A*STAR, Singapore, Singapore (Bosman, M.) \|\| Dipt. di Sci. e Metodi dell'Ing., Univ. di Modena e Reggio Emilia, Modena, Italy (Padovani, A.; Larcher, L.)
Abstract	Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer $SiO_{2}/SiON$ stacks, the number of possible scenarios of post-BD increases when analyzing high-κ-interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above/below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Å stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.
Sponsorship	IEEE Electron Devices Soc.
File Size	949710
File Format	PDF
ISBN	9781479901128
ISSN	19381891
e-ISBN	9781479901135
e-ISBN	9781479901111
DOI	10.1109/IRPS.2013.6532020
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electric breakdown Degradation Metals Dielectrics Stress Logic gates Monte Carlo methods Wear-out Filamentation Percolation Post breakdown Soft breakdown Thermochemical maodel Trap generation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Real-time analysis of ultra-thin gate dielectric breakdown and recovery - A reality

An overview of physical analysis of nanosize conductive path in ultrathin SiON and high-к gate dielectrics in nanoelectronic devices

Modeling the breakdown statistics of gate dielectric stacks including percolation and progressive breakdown

Identifying the First Layer to Fail in Dual-Layer ${rm SiO}_{rm x}/{rm HfSiON}$ Gate Dielectric Stacks

Reliability, degradation and breakdown of advanced gate stacks

Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks

Spectroscopy of SILC trap locations and spatial correlation study of percolation path in the high-κ and interfacial layer

Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks

Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks

Similar Documents

Real-time analysis of ultra-thin gate dielectric breakdown and recovery - A reality

An overview of physical analysis of nanosize conductive path in ultrathin SiON and high-к gate dielectrics in nanoelectronic devices

Modeling the breakdown statistics of gate dielectric stacks including percolation and progressive breakdown

Identifying the First Layer to Fail in Dual-Layer ${rm SiO}_{rm x}/{rm HfSiON}$ Gate Dielectric Stacks

Reliability, degradation and breakdown of advanced gate stacks

Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks

Spectroscopy of SILC trap locations and spatial correlation study of percolation path in the high-κ and interfacial layer

Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks

Soft breakdown free atomic-layer-deposited silicon-nitride/SiO/sub 2/ stack gate dielectrics

The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks