NDLI: Accelerated stress testing methodology to risk assess silicon-package thermomechanical failure modes resulting from moisture exposure under use condition

Content Provider	IEEE Xplore Digital Library
Author	Rangaraj, S. Daeil Kwon Min Pei Hicks, J. Leatherman, G. Lucero, A. Wilson, T. Streit, S. Jun He
Copyright Year	2013
Description	Author affiliation: Technol. Dev. & Manuf. Quality & Reliability, Intel Corp., Hillsboro, OR, USA (Rangaraj, S.; Daeil Kwon; Min Pei; Hicks, J.; Leatherman, G.; Lucero, A.; Wilson, T.; Streit, S.; Jun He)
Abstract	IC components are exposed to moisture and thermal cycles during chip-package-board assembly and in their end use conditions. Moisture exposure influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. Reliability performance under accelerated stresses that simulate use conditions are often a critical factor in choice of materials, processing options and design rules. A complete assessment of the cumulative environmental exposure from chip-package assembly, shipment/storage, board system assembly, through end-customer use is required to guarantee product performance and reliability. This paper will detail these end user environments and use failure mode/mechanism specific acceleration models to develop accurate accelerated life testing plans and requirements. These requirements will then be compared to JEDEC standards based requirements and a need for re-calibration of these standards to more appropriate temperatures and stress durations will be highlighted.
Sponsorship	IEEE Electron Devices Soc.
File Size	347050
File Format	PDF
ISBN	9781479901128
ISSN	19381891
e-ISBN	9781479901135
e-ISBN	9781479901111
DOI	10.1109/IRPS.2013.6532032
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Moisture Stress Standards Reliability Acceleration Materials Mathematical model JEDEC standard moisture use conditions acceleration model HAST thermal cyclin
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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