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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yong, Zhenzhong Li, Hengfu Zhang, Wenqi |
| Copyright Year | 2014 |
| Description | Author affiliation: The National Center for Advanced Packaging Co., Ltd. (NCAP China) Wuxi, 214139, China (Yong, Zhenzhong; Li, Hengfu; Zhang, Wenqi) |
| Abstract | The dielectric insulation layer is critical to the TSV package reliability and the process of forming sidewall insulation of through silicon via (TSV) was a challenging bottleneck in 3D integration. In this paper, dielectric insulation layers in TSV with aspect ratio of 10:1 were fabricated by PECVD tetraethyl orthosilicate (TEOS) process and thermal oxidation process. The morphology and step coverage of the dielectric insulation layers were characterized using field emission scanning electron microscopy (FESEM). The electrical performance of blanket PECVD TEOS films and thermal oxide films were investigated by mercury probe Voltage-current (I-V) and Capacitance — Voltage (C-V) measurements. The PECVD TEOS films show good conformality, high breakdown voltage and low current leakage. The thermal oxide films have higher step coverage of almost 100% and lower leakage current. By combining PECVD TEOS process and thermal oxidation process, dual thermal oxide/PECVD TEOS insulation layers with high step coverage are fabricated. |
| Starting Page | 684 |
| Ending Page | 687 |
| File Size | 2371389 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479969944 |
| DOI | 10.1109/EPTC.2014.7028393 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-12-03 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Films Through-silicon vias Insulation Oxidation Silicon Dielectrics Leakage currents |
| Content Type | Text |
| Resource Type | Article |
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