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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tang, Tom Lan, Albert Tsai, Jensen Chang, Ivan Chen, Evan |
| Copyright Year | 2014 |
| Description | Author affiliation: Siliconware Precision Industries Co., Ltd. No. 153, Sec. 3, Chung-Shan Rd. Tantzu Taichung 427, Taiwan, R.O.C. (Tang, Tom; Lan, Albert; Tsai, Jensen; Chang, Ivan; Chen, Evan) |
| Abstract | In the recent years, compact, slim and lightweight mobile electronics are requested from customers. Miniaturization of IC packaging has been a must. Coreless substrate technology is the key to achieve it. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layer to interconnect chip and the motherboard. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame and pre-molding compound techniques has aroused lots of attention in IC semiconductor industry. Its trace is plated on the metal carrier and is embedded by molding compound. By using this unique embedded trace technology, it makes the fine-line of having 20um/20um or 15um/15um line width/space and having no concern for high cost. However, without rigid substrate core material supporting, the major challenges of this coreless substrate come from the warpage throughout substrate manufacturing and assembly process. In order to diminish the warpage, lots of experiments were conducted and discussed in this paper. Thermal performance and mechanical stress simulations also were employed to establish the package structure and also to narrow down the row material selections, including die thickness decision, pre-molding and molding compound selection (which focus on its CTE and Tg adjustments). Screen and corner DOEs which includes molding compounds, die-bond reflow profile and post-mold cure parameters were performed to come out the optimal material and process window. Reliability and functional tests have been passed as well. Hence, this pre-molded coreless substrate has been proven to be a feasible and reliable way for the miniaturization in assembly industry. |
| Starting Page | 200 |
| Ending Page | 203 |
| File Size | 536713 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479969944 |
| DOI | 10.1109/EPTC.2014.7028305 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-12-03 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Substrates Compounds Assembly Flip-chip devices Reliability Electronic packaging thermal management |
| Content Type | Text |
| Resource Type | Article |
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