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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ai-Chie, Wang Hui, Chong Chin |
| Copyright Year | 2014 |
| Description | Author affiliation: Micron Semiconductor Asia Pte. Ltd. 1 North Coast Drive, Singapore 757432 (Ai-Chie, Wang; Hui, Chong Chin) |
| Abstract | As the speed performance of memory silicon die advances over the generations, the corresponding package designs must align with the desired package-level performance. This has driven package designers to adopt the appropriate package routing design practices for DDR2 to DDR4 DRAM and NV-DDR to NV-DDR2 NAND Flash memory packages that keep not only the mechanical integrity of the package in mind but also the electrical (signal integrity) aspects of the package. This paper describes the relevant package routing considerations for BOC and COB interposer designs with the goal of meeting the electrical requirements for high-speed devices; these results have been documented to ensure that these routing requirements are checked at the final design review stage to enable Micron to deliver quality products to customers. |
| Starting Page | 774 |
| Ending Page | 779 |
| File Size | 918083 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479969944 |
| DOI | 10.1109/EPTC.2014.7028309 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-12-03 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Layout Substrates Wires Silicon Impedance Flash memories |
| Content Type | Text |
| Resource Type | Article |
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