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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jung, Boo Yang Ho, David Soon Wee Sorono, Dexter Velez Lim, Sharon Pei Siang Chen, Zhaohui Yong, Han Lin, Bu Chong, Chai Tai |
| Copyright Year | 2014 |
| Description | Author affiliation: Institute of Microelectronics, A∗STAR (Agency for Science, Technology, and Research) 11 Science Park Rd, Singapore Science Park II, Singapore 117685 (Jung, Boo Yang; Ho, David Soon Wee; Sorono, Dexter Velez; Lim, Sharon Pei Siang; Chen, Zhaohui; Yong, Han; Lin, Bu; Chong, Chai Tai) |
| Abstract | Currently PoP (Package on Package) has become a main stream of 3D integration for logic devices such as baseband and application processors with high performance memory in mobile application. This PoP has an advantage of a smaller package size with high functionality due to stacking of two different packages. However a conventional PoP with PCB substrate has a limitation to meet the recent requirement of a low profile with high performance in the thin mobile application. A fan out wafer level packaging is one of promising solution to meet a low profile with high performance. The direct solder attach on the RDL layer in the wafer level package provide a low profile package and RDL formation beyond Si die area provide a high performance with allowing higher solder ball counts. Also an embedded passive into fan out wafer level package is able to provide the better performance as well as flexibility to extend to SiP (System in Package). In this study, a low profile fan out Package on Package was successfully demonstrated with 14.0×14.0mm of a bottom package and 8.0×8.0mm of top package as well as embedded passives. The top and bottom package were electrically connected through TMV (Through Mold Via) with electro-less plating. TMV (Through Mold Via) was characterized with various EMC materials such as filler size, contents and resin material. The optimization of passive component location in term of process and reliability was performed using mold flow simulation. Also an assembly process was developed to minimize the package warpage using thermo-mechanical simulation. |
| Starting Page | 597 |
| Ending Page | 600 |
| File Size | 459150 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479969944 |
| DOI | 10.1109/EPTC.2014.7028373 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-12-03 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Electromagnetic compatibility Shape Stacking Assembly Packaging Electronics packaging Three-dimensional displays |
| Content Type | Text |
| Resource Type | Article |
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