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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chen, Miaowen Huang, Leo Pan, George Kao, Nicholas Jiang, Don Son |
| Copyright Year | 2014 |
| Description | Author affiliation: Siliconware Precision Industries Co., Ltd. Tantzu, Taichung, Taiwan (Chen, Miaowen; Huang, Leo; Pan, George; Kao, Nicholas; Jiang, Don Son) |
| Abstract | With the need for more functionality, smaller form factor and high-speed data transfer rate, the application processor of tablet PC need more power to serve the electrical function requirements. Therefore, the high thermal performance of package design to ensure tablet CPU operating under safe temperature environment becomes a primary challenge for heat management. The package-on-package (PoP) stacking assembly is constructed by individual fabricated and tested packages from the same or different supplier provided in a stacking structure through solder joints. It can reduce the placement and routing areas on board and reach limits in logic-to-memory bandwidth, becomes more and more popular in tablet devices. In this paper, we investigate the thermal characteristic of PoP package in tablet system, especially on the thermal interactions between top and bottom packages. Since tablet application is running, it is usually found that bottom package has higher die junction temperature with higher power and impacts top memory package to exceed safe operating temperature. The system level thermal model of PoP structure was set up by using computational fluid dynamics (CFD) modeling technique and considered with different package and die size, TIM (thermal interface material), compound and under-fill material effects in order to find out optimal BOM and dimension guidelines. The PoP structure consists of bottom Flip-Chip Chip Scale Package (FCCSP) and top Thin Fine pitch Ball Grid Array package (TFBGA) stacking through solder joints schematically. While top TFBGA package is mounted on bottom FCCSP package, controlling component warpage is also a very important issue. The excessive warpage could induce failure on stacking process. The bottom FCCSP package warpage characteristics are further to analysis for structure and material properties effects. Furthermore, employing suitable BOM and dimension leads FCCSP package assembly to achieve warpage less than 4 mil from reflow temperature to room temperature. For DOE simulation, we assume some input power of top and bottom packages to evaluate the die junction temperature variation and find PoP package with external metal heat sink can perform the best thermal performance, which has about 22.6 % temperature improvement in tablet system. |
| Starting Page | 837 |
| Ending Page | 840 |
| File Size | 169715 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479969944 |
| DOI | 10.1109/EPTC.2014.7028280 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-12-03 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Electronic packaging thermal management Temperature Junctions Compounds Materials Metals Thermal conductivity |
| Content Type | Text |
| Resource Type | Article |
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