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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cadacio, F. Rebibis, K. J. Capuz, G. Daily, R. Gerets, C. Sleeckx, E. Duval, F. Wang, T. Miller, R. A. Beyer, G. Beyne, E. |
| Copyright Year | 2014 |
| Description | Author affiliation: IMEC, Kapeldreef 75, B-3001 Leuven, Belgium (Cadacio, F.; Rebibis, K. J.; Capuz, G.; Daily, R.; Gerets, C.; Sleeckx, E.; Duval, F.; Wang, T.; Miller, R. A.; Beyer, G.; Beyne, E.) |
| Abstract | With the emergence of 3D technology to answer the challenging limits of Moore's Law, certain features in today's 3D IC packages have to be adopted in order to meet the reliability and robustness of this technology. The barriers used for TSV processing, the metallurgy of the μbump, the underfill material used in stacking in combination with the IC assembly materials all play a vital role in the reliability and robustness of a 3D IC package. One of the materials selected for assembly in this 3D package was the underfill between the stacked dies. The underfill provides the mechanical stability for micro-bumps and prevents moisture between the resulting gaps between dies before the 3D stack is sent for packaging. Underfilling options for 3D IC stacks differs significantly to what has been a standard in the industry which is in using capillary underfills. Stacking of the 3D device is currently done using a thermocompression process, which is quite different from the mass reflow chip attach process normally done in the industry. This is mainly due to the narrow gaps and very fine bump pitches of 3D ICs. As a result of these fine and narrow geometry change in 3D stacks, it is quite difficult to use the capillary underfill process in combination with the thermo-compression bonding process. The use of pre-applied underfills such as the Wafer Level Underfills (WLUFs) and No Flow Underfills (NUFs) in combination with the thermo-compression bonding process has shown to be a viable solution for 3D stacking. Using No-Flow Underfills (NUF) in thermo-compression bonding also introduce processing complexities (see Figure 1.0). The complexity lies in dispensing a very accurate volume to fill a gap lower than 15um., in most cases, the amount of underfill material that needs to be dispense is in the submilligram level. Dispensing this amount of material requires very accurate jet dispensers and will need a lot of characterization in terms of jetting the NUFs. By using Wafer Level Underfills (WLUFs) takes out the complexity of figuring out the correct jetting parameters in order to fill the entire UF gap. But there are several aspects of the said material that needs to be taken into consideration such as its transparency (see Figure 2.0), thickness variations storage/staging conditions and melt viscosity all of which play important roles in making the material useable for 3D stacks. Selection of the correct mold compound to be used for the 3D package is also deemed very important in terms of the reliability performance of the package. The CTE and warpage behavior of the mold compound had to be evaluated and quantified in the selection process (see Figure 3.0). In this paper, the selection process of Wafer Level Underfill and low CTE mold compound materials and the resulting package reliability of the combination of these materials will be shown and discussed. Jedec standard reliability tests (MSL, TCT-B, HTS and PCT) were used in quantifying the reliability performance of the 3D package. Electrical tests on the daisy chain of the test vehicle and package robustness in terms delamination in the interfaces of the package were checked during the different reliability readouts. |
| Starting Page | 444 |
| Ending Page | 448 |
| File Size | 835193 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479969944 |
| DOI | 10.1109/EPTC.2014.7028355 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-12-03 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Three-dimensional displays Materials Stacking Compounds Semiconductor device reliability Lamination |
| Content Type | Text |
| Resource Type | Article |
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