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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tseng, A. Lin, M. Hu, B. Chen, J.W. Wan, J.M. Lee, S. Yi-Shao Lai |
| Copyright Year | 2010 |
| Description | Author affiliation: ASE (US), Inc., 1255 E. Arques Ave., Sunnyvale, CA 94085, USA (Tseng, A.) || ASE, Inc., 26 Chin 3rd Rd., Nantze Export Processing Zone, Kaohsiung 811, Taiwan (Lin, M.; Hu, B.; Chen, J.W.; Wan, J.M.; Lee, S.; Yi-Shao Lai) |
| Abstract | The advanced Quad Flat No-Lead (aQFN) package is an enhanced version of conventional QFN with multiple row terminals of featuring higher number of I/O ports. The aQFN thermal and electrical performance are superior due to smaller profile and shorter interconnects and the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of the higher package standoff. aQFN provides similar I/O number approaching that of a BGA-type chip-scale package (FBGA) but much less cost since the expensive substrate is replaced by lead frame. aQFN turns out to be an ideal low cost solution for electrical components of portable telecommunication applications such as IrDA, blue-tooth, RFID, cell phone baseband etc. for its superior thermal, electrical, reliability performances and miniaturized package size, With such advantages, the replacement of FBGA with aQFN in low up to medium lead-count applications is therefore highly expectable, especially for handheld & PDA devices with its related applications. With such higher pin-count, multi-row and small terminal pitch than QFN, how to design the aQFN package terminals for printed circuit board layout and the stencil patterning and opening for solder paste printing become crucial issues. aQFN will be introduced in terms of its application advantages, development, fabrication process flow, SMT process with stencil design guideline for surface mount assembly yield. Finally, “Surface Mount Application Notes” have been issued. |
| Starting Page | 737 |
| Ending Page | 742 |
| File Size | 2534769 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424485604 |
| e-ISBN | 9781424485628 |
| e-ISBN | 9781424485611 |
| DOI | 10.1109/EPTC.2010.5702735 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-08 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Electronic packaging thermal management Assembly Lead Packaging Fabrication Surface treatment Copper |
| Content Type | Text |
| Resource Type | Article |
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