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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tu Anh Tran Dorinski, D. Gonzales, S. Phong Vu Yow, K.Y. |
| Copyright Year | 2010 |
| Description | Author affiliation: Freescale Semiconductor, Inc., 6501 William Cannon Drive, Austin TX 78735, USA (Tu Anh Tran) || Freescale Semiconductor, Inc., No.2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, Selangor, Petaling Jaya, 47300, Malaysia (Yow, K.Y.) || Freescale Semiconductor, Inc., 1300 North Alma School Road, Chandler, Arizona 85224, USA (Dorinski, D.; Gonzales, S.; Phong Vu) |
| Abstract | All market segments continue to put cost pressure on semiconductor and packaging suppliers in order to stay competitive. Taking advantage of continuing silicon innovation in fabrication process, silicon area reduction and more device functionalities increase potential die count per wafer and lower the die cost. Staying in wire bond packaging instead of migrating to flip chip packaging further provides a cost competitive advantage. Wire bond packaging for silicon devices has been the backbone of the semiconductor industry to serve communications, automotive and networking customers for many years. Innovative interconnect routing and IC design and fine pitch wire bonding capability enable silicon to have 900 bonding pads in an area of $60mm^{2}.$ High wire count and wire density is unprecedented in thermally enhanced plastic ball grid array (TE-PBGA) packages with an internal heat spreader, which is commonly denoted as TE-PBGA-II. With further shrink of the silicon dimension, low-k inter-layer dielectric (ILD) material has been widely used to replace the traditional SiO2 ILD in order to reduce the interconnect delay. Low-k dielectric by definition has a dielectric value of less than 3. The introduction of low-k ILD material into silicon imposes new challenges for high wire density packaging. In particular, the inherently weak adhesion in the low-k interconnect makes the silicon more susceptible to a failure mode called ILD crack or delamination that causes electrical failure during temperature cycling test. This paper will discuss challenges and resolution during the packaging development for low-k products with high wire density in large 31×31 and 35×35mm TE-PBGA-II packages. Challenges range from wafer dicing through difficult test structures in the scribe streets, die attach fillet height control, wire bonding on low-k bond pads, and molding low-k silicon in a large PBGA package with an internal heat spreader. Alternative methods including Finite Element Modeling and extended package reliability testing were used to demonstrate the robustness of the low-k packaging solution. |
| Starting Page | 179 |
| Ending Page | 184 |
| File Size | 3021171 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424485604 |
| e-ISBN | 9781424485628 |
| e-ISBN | 9781424485611 |
| DOI | 10.1109/EPTC.2010.5702629 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-08 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delamination Wire Blades Compounds Stress Silicon Heating |
| Content Type | Text |
| Resource Type | Article |
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