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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sharma, G. Seung Wook Yoon Prashant, M. Emigh, R. Sin Jae Lee Kai Liu Pendse, R. |
| Copyright Year | 2010 |
| Description | Author affiliation: STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 (Sharma, G.; Seung Wook Yoon; Prashant, M.) || STATS ChipPAC Inc.47400 Kato Road Fremont, CA 94538 USA (Pendse, R.) || STATS ChipPAC Korea Ltd. Ichon, Kyunggi-Do, Korea 467-701 (Sin Jae Lee) || STATS ChipPAC Inc 1711 W Greentree Dr. Tempe, AZ 85284-2713, USA (Emigh, R.; Kai Liu) |
| Abstract | The drive for small form factor and foot print area packages is being fueled by consumer electronic applications that today constitute 50% of semiconductor revenue. Mobile phones are experiencing explosive growth both in terms of unit shipments and increased complexity at the same time. In just one decade mobile phone has transformed from a simple communication device into more complex system integrating features that allow customers to use it as a multipurpose gadget. Small form factor, foot print areas and cost effective technology are mandatory characteristics for packages in hand held electronic applications. Demand for WLP is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. However there are some restrictions in possible applications for fan-in WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. This paper will highlight some of the recent characterization works of electrical, thermal and mechanical performance of eWLB packaging. The performance is compared with fcFBGA packaging format. Thermal characterization activity is carried out to investigate the effect on eWLB configuration with power loading. Thin film based integrated passives on the fan-out area (mold material) of the eWLB is also analyzed during electrical characterization. Due to the low-loss property of the mold material, plated Cu inductors showed high quality-factor (Q) performance. The mold material in fan-out area is not only used as a supporting substrate, but also serves as the package substrate, which allows the high-Q inductors to be implemented with other RF chips in one single package. Parasitic electrical performance and characterization works will be presented in this paper. eWLB package warpage behavior with temperature profile observed with Thermo-Moire method, package and board level reliability results will be presented in this paper too. |
| Starting Page | 211 |
| Ending Page | 216 |
| File Size | 1391236 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424485604 |
| e-ISBN | 9781424485628 |
| e-ISBN | 9781424485611 |
| DOI | 10.1109/EPTC.2010.5702635 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-08 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Packaging Inductors Substrates Electronic packaging thermal management Three dimensional displays Temperature measurement |
| Content Type | Text |
| Resource Type | Article |
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