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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chu-Chung Lee Tu Anh Tran Yuan Yuan Chin Teck Siong |
| Copyright Year | 2010 |
| Description | Author affiliation: Freescale Semiconductor Inc., No.2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, Selangor, Petaling Jaya, 47300, Malaysia (Chin Teck Siong) || Freescale Semiconductor Inc., 6501 William Cannon Drive West, MD: TX30-OE21: Austin, TX 78735, USA (Chu-Chung Lee; Tu Anh Tran) || Freescale Semiconductor Inc., 7700 West Parmer Lane, MD: TX32-PL49, Austin, TX 78729, USA (Yuan Yuan) |
| Abstract | The cavity-down thermally enhanced package such as Tape Ball Grid Array (TBGA) has the best thermal performance among the high pin count wire bonded package types because the silicon is attached directly onto a thick internal heat spreader. The TBGA package with low-k/Cu wafers has however challenged the assembly industry in passing package qualification requirement especially temperature cycling requirement. Low-k interlayer dielectric (ILD) material usually has the dielectric constant k of less than 3. The inherently weak adhesion in the low-k interconnect stack-up makes the silicon more susceptible to a failure mode called ILD crack or delamination that causes electrical failure during temperature related excursion such as temperature cycling test and board-level mounting. ILD delamination failure was reported not only at the die corner with highest stress concentration, but also on the die side away from the corner. Optical inspection of dicing quality at failing areas showed similar level of back-end-of-line (BEOL) peeling through scribe test structures that would have passed reliability testing when assembling in a conventional plastic ball grid array (PBGA). Mechanical analyses were performed to identify the specific failing interface within the stack of the back-end-of-line (BEOL) in the low-k die. 3D finite element model simulations were performed to analyze the stress distribution in the low-k die area. Structural parameters of the cavity-down TBGA package were modulated. The simulation analysis indicated that TBGA package applies a tensile stress on the top portion of the die edge region where the inter-layer dielectric (ILD) stacks are located when the package is subjected to temperature cycling tests. The tensile stress on the top portion of the die can be reduced by varying specific structural parameters of the TBGA package. A series of experiments was designed and conducted to validate the prediction of the mechanical simulation model. The simulation analysis supported by empirical data explained as to why the TBGA package is more susceptible to ILD delamination failures in temperature excursion condition in the presence of or lack of dicing defects. A special low stress glob top material was formulated and demonstrated a good production capability and package level reliability. The knowledge of the stress distribution in the TBGA system enabled the development of low stress glob top encapsulant that demonstrated a good production capability and package level reliability. |
| Starting Page | 62 |
| Ending Page | 67 |
| File Size | 3123687 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424485604 |
| e-ISBN | 9781424485628 |
| e-ISBN | 9781424485611 |
| DOI | 10.1109/EPTC.2010.5702606 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-08 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stress Delamination Copper Electronics packaging Dielectric materials |
| Content Type | Text |
| Resource Type | Article |
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