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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Liu Ying Ying Premachandran, C.S. Seung Wook Yoon Liao Ebin Nagarajan, R. Ramana, P.V. |
| Copyright Year | 2007 |
| Description | Author affiliation: Inst. of Microelectron., Singapore (Liu Ying Ying; Premachandran, C.S.; Seung Wook Yoon; Liao Ebin; Nagarajan, R.; Ramana, P.V.) |
| Abstract | 80 wt.% Au, 20 wt.% Sn solder is used in optoelectronics because it allows soldering in fluxless processes. Au-Sn solder is also applied in the field of RF and MEMS packaging. Normally the deposited solders are re-flowed after electroplating but it is also possible to use the bumps in the as-deposited condition. Au-Sn solder which has been reflowed consists of an Au pedestal with a eutectic solder cap on top. Reflow soldering is a cost effective approach for the flip chip technology or die attachment process. Using pick & place equipment the substrate is populated with the components. Soldering is performed afterwards in an oven. During soldering it is possible to utilize the self-alignment mechanism. In this study, Au-Sn besides 80 wt.% Au, 20 wt.% Sn solder composition is evaluated and characterized in evaporation deposition process for SiOB (silicon optical bench) applications. Multiple layers of thin Sn and Au solders are deposited one-by-one. The layer thickness is calculated and optimized to meet the desired solder composition. The deposited solder is evaluated using FIB (Focused Ion Beam) to observe the layer thickness uniformity. Micro-structural observations for deposited solder samples are conducted before and after solder reflow for melting. The composition is identified by chemical composition analysis (EDS - energy dispersive spectroscopy) and thermal analysis (DSC - differential scanning calorimetry). The interfacial reaction and morphology with Ti/Pt/Au UBM (under bump metallurgy) layers are also observed with different reflow conditions. Results of die shear for photonic diode attachment are shown. |
| Starting Page | 370 |
| Ending Page | 373 |
| File Size | 1148167 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424413249 |
| DOI | 10.1109/EPTC.2007.4469823 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-12-10 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Packaging Gold Tin Chemical analysis Radio frequency Micromechanical devices Reflow soldering Costs Flip chip Ovens |
| Content Type | Text |
| Resource Type | Article |
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