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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhiyuan, Y.J. |
| Copyright Year | 2007 |
| Description | Author affiliation: Peregrine Semicond., San Diego (Zhiyuan, Y.J.) |
| Abstract | Peregrine's silicon on sapphire technology provides high performance RF IC devices to wireless market, while for bumping on this type of sapphire wafer new challenges will be encountered. High residual stress accumulated on sapphire wafer surface may cause bumping reliability performance issue. Sapphire wafer's singulation process, which uses three-point breaking method, requires bumping must be of a reasonable structure to achieve high mechanical strength. Through bumping structure design and process planning, all the encountered issues have been solved. The bumping process by lead-free solder paste printing method and the bumping structure design proposed in this paper provides a volume production solution for sapphire wafer. |
| Starting Page | 902 |
| Ending Page | 905 |
| File Size | 544622 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424413249 |
| DOI | 10.1109/EPTC.2007.4469766 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-12-10 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Environmentally friendly manufacturing techniques Lead Printing Silicon Radio frequency Radiofrequency integrated circuits Residual stresses Process design Process planning Production |
| Content Type | Text |
| Resource Type | Article |
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