NDLI: Designing Underfill Material in Resolving Package High Coplanarity Issues

Content Provider	IEEE Xplore Digital Library
Author	Yin, B.Y.W.
Copyright Year	2007
Description	Author affiliation: Intel Technol., Kulim (Yin, B.Y.W.)
Abstract	In recent years, chipsets are doing more functions as compared to few years ago. As a result, the package form factor has to increase to accommodate the added functions. During the development of flip chip ball grid array generation X (FCBGA-x), high coplanarity yield loss was observed on test vehicle of die size 550 sq mils and form factor of 42.5 sq mm. Aside from the coplanarity yield loss, it also posed a reliability concern especially post motherboard reflow. This has raise concern to the platform. Few options were proposed to mitigate this yield loss. Amongst the options being explored include tightening the technology target specifications (TTS) envelope, variable solder resist opening (VSRO), restrainer, using head spreader lids, alternative underfill (UF) material or process and also combination options, i.e. VSRO. The ideal case is to improve coplanarity without any cost adder, either from material or process, standpoint. In order to minimize the coplanarity yield loss, a breakthrough solution is needed. Through empirical data collected from previous platforms, one of the key contributors that increased the package coplanarity was during epoxy cure. With strong understanding of materials and process interactions, a team was formed to march towards formulating an innovative underfill material. There is a balancing act required during the development process. By reformulation of the underfill material and change of the cure recipe, an improvement of package coplanarity is anticipated. At the same time, there will be also unknown reliability risks die level and die crack performance. Hence, there is a need to consider all the tradeoffs when selecting the underfill formulation. With a strong team work within Intel & with Supplier, 4 underfill iterations were successfully put to the test. An underfill has successfully made an improvement of 1 mil to the coplanarity, bringing down the yield loss significantly based on 4 DOEs. This paper documents the challenges in enabling this underfill to mitigate coplanarity yield loss, as well as the reliability data.
Starting Page	636
Ending Page	639
File Size	317410
Page Count	4
File Format	PDF
ISBN	9781424413249
DOI	10.1109/EPTC.2007.4469681
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-10
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Yield estimation Flip chip Electronics packaging Mesh generation Vehicles Speech synthesis Resists Costs Soldering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Underfill swelling and temperature-humidity performance of flip chip PBGA package

Evaluating underfill material for flip chip ball grid array package

Molded underfill technology for low-k flip chip packages

Flip chip underfill reliability of CSP during IR reflow soldering

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The effects of underfill and its material models on thermomechanical behaviors of flip chip package

Underfill material requirements for reliable flip chip assemblies

High Reliability and Thermal Performance FCBGA Package

An analytical model for predicting the underfill flow characteristics in flip-chip encapsulation

Designing Underfill Material in Resolving Package High Coplanarity Issues

Similar Documents

Underfill swelling and temperature-humidity performance of flip chip PBGA package

Evaluating underfill material for flip chip ball grid array package

Molded underfill technology for low-k flip chip packages

Flip chip underfill reliability of CSP during IR reflow soldering

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The effects of underfill and its material models on thermomechanical behaviors of flip chip package

Underfill material requirements for reliable flip chip assemblies

High Reliability and Thermal Performance FCBGA Package

An analytical model for predicting the underfill flow characteristics in flip-chip encapsulation

Designing Underfill Material in Resolving Package High Coplanarity Issues