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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yuan Lin Tzeng Kao, N. Eason Chen Jeng Yuan Lai Yu Po Wang Hsiao, C.S. |
| Copyright Year | 2007 |
| Description | Author affiliation: Siliconware Precision Ind. Co. Ltd., Taichung (Yuan Lin Tzeng; Eason Chen; Jeng Yuan Lai; Yu Po Wang; Hsiao, C.S.) |
| Abstract | In recent years, miniaturization, lightening, high performance, high reliability and low cost have been demanded intensely for electronic products, especially in the rapid growth of portable cell phone domain. Furthermore, multiple functional demand induces advanced package developments, such as system-on-chip (SoC) and system-in-package (SiP). System-on-chip (SoC) is an ideal package to integrate multiple functionalities in the chip level. However, the design and testing are very difficult, high cost and low manufacturing yield, these reasons drives multiple functional integration technology toward system-in-package (SiP) development gradually. The package-on-package (PoP) stacking assembly is a member of the SiP family. It is constructed by individual fabricated and tested packages from the same or different supplier provided in a stacking structure through solder joints. It can reduce the placement and routing areas on board and also allow one damaged component to be replaced which is opposite to stacked Chip Scale Package (SCSP). This paper aims to investigate warpage and stress characteristic analyses for PoP configuration by using finite element method (FEM). The structure consists of bottom PBGA package and top TFBGA package stacking through solder joints. While top TFBGA is mounted on bottom PBGA, controlling component warpage is a very important issue. The excessive warpage could induce failure on stacking process. In this study, firstly, we focus on bottom PBGA warpage investigation for package and die size, die and substrate core thickness, compound and substrate core material properties effects in order to find out optimized BOM and dimension guidelines. Furthermore, employing suitable BOM and dimension leads PBGA package assembly to achieve warpage less than 4 mil. The experimental result agrees above target very well finally. Secondly, PoP module warpage and ball stress characteristics are further to analysis as the next topic. For fixed bottom PBGA package from above-mentioned finding design and combination, module warpage and ball stress trends are investigated to take as PoP design guidelines with top TFBGA die size and stacked die number effects. For summarized results, the top TFBGA with 7 times 9 mm2 die size can reduce 24% module warpage compared to 11 times 13 mm2. The TFBGA with single die can reduce 29% module warpage than 4 stacked dice. Shrinking chip size and decreasing die stacked number can be recommended to reduce module warpage and board level ball stresses effectively including TFBGA and PBGA balls. Finally, we will investigate top TFBGA mold thickness effect on PoP structure to minimize module warpage and ball stresses. |
| Starting Page | 482 |
| Ending Page | 487 |
| File Size | 438728 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424413249 |
| DOI | 10.1109/EPTC.2007.4469725 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-12-10 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stress Stacking Electronics packaging System-on-a-chip Assembly Soldering Bills of materials Guidelines Costs Cellular phones |
| Content Type | Text |
| Resource Type | Article |
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