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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tong Yan Tee Siew, G. Haoyang Chen Soh, S. In Soo Kang Jong Heon Kim Teck Kheng Lee Bok Leng Ser Hun Shen Ng Hoe, G. Shan Gao |
| Copyright Year | 2011 |
| Description | Author affiliation: SMARTS Technology LLP. Blk 425, Canberra Road, #11-477, Singapore 750425 (Hun Shen Ng) || Nepes Pte Ltd. 12 Ang Mo Kio Street 65, Singapore 569060 (Tong Yan Tee; Siew, G.; Haoyang Chen; Soh, S.; In Soo Kang; Jong Heon Kim) || Institute of Technical Education. 201 Circuit Road, Singapore 379498 (Teck Kheng Lee; Bok Leng Ser) || Institute of Microelectronics. 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Hoe, G.; Shan Gao) |
| Abstract | Wafer level package (WLP) provides the smallest form factor to satisfy multifunctional device requirements along with improved signal integrity for today's latest handheld electronics. WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Three sizes of LCWLP are designed and simulated, prior to assembly and reliability tests. The structural design features electrical, mechanical and thermal simulations of LCWLP with three chip sizes and ball layout. Simulation results show LCWLPs investigated are able to satisfy the functional and reliability requirements. Electrical simulation demonstrates that LCWLP with the same I/O counts but smaller package size, has better functional performance than FCBGA. Mechanical simulation indicates that wafer level warpage of all LCWLPs studied are within acceptable range for wafer level processes. For board level reliability, LCWLPs are expected to pass the thermal cycling test. Furthermore, LCWLPs are small in sizes with very low junction-to-case thermal resistance, able to keep the maximum junction temperature low and cool the chips during operations. Its thermal performance is strongly influenced by the chip size but independent of the Cu RDL density. |
| Starting Page | 1 |
| Ending Page | 7 |
| File Size | 4774559 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781457717703 |
| e-ISBN | 9781457717697 |
| e-ISBN | 9781457717680 |
| DOI | 10.1109/ICEPT.2011.6066896 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-08 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Resistance Copper Electronic packaging thermal management Junctions Semiconductor device modeling Semiconductor device reliability |
| Content Type | Text |
| Resource Type | Article |
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