NDLI: Scalability of a trench capacitor cell for 64 Mbit DRAM

Content Provider	IEEE Xplore Digital Library
Author	Shen, B.W. Chung, G. Chen, I.C. Coleman Jr., D.J. Ying, P.S. McKee, R. Yashiro, M. Teng, C.W.
Copyright Year	1989
Description	Author affiliation: Texas Instrum., Dallas, TX, USA (Shen, B.W.; Chung, G.; Chen, I.C.; Coleman, D.J., Jr.; Ying, P.S.; McKee, R.; Yashiro, M.; Teng, C.W.)
Abstract	The authors address cell leakage issues and conclude that a unique field-plate isolated trench capacitor cell structure, already demonstrated at the 16-Mb level with over 1 s of data retention (50% bit fail measured at 90 degrees C), is scalable to 64-Mb DRAM (dynamic RAM). As the trench size is reduced to 0.6 mu m, the trench curvature helps reduce the trench-to-trench punch-through leakage. Substrate concentration of approximately 10/sup 17/ cm/sup -3/ is sufficient to suppress the punch-through current with a 0.5- mu m trench spacing. Diode and gate-induced breakdown voltages remain well above the operating voltage. Trench capacitor dielectric is scalable to less than 5-nm equivalent oxide thickness.<>
Starting Page	27
Ending Page	30
File Size	407368
Page Count	4
File Format	PDF
ISBN	0780308174
ISSN	01631918
DOI	10.1109/IEDM.1989.74221
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-12-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Scalability Capacitors Random access memory Dielectric substrates Capacitance Semiconductor diodes Space technology Implants Dielectrics and electrical insulation Instruments
Content Type	Text
Resource Type	Article
Subject	Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering

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