NDLI: Design of a wideband low power FMCW synthesizer in 65 nm CMOS for radar applications

Content Provider	IEEE Xplore Digital Library
Author	Supeng Liu Yuanjin Zheng Xiaofeng He
Copyright Year	2014
Description	Author affiliation: Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore (Supeng Liu; Yuanjin Zheng; Xiaofeng He)
Abstract	The paper presents a design of a low power wide output bandwidth FMCW frequency synthesizer for radar applications. The proposed FMCW frequency synthesizer adopts digital phase locked loop approach and has been implemented in 65 nm CMOS technology. A phase domain model is proposed for analyzing the digital phase locked loop architecture. The FMCW synthesizer is able to generate triangularly modulated continuous wave of 3GHz output bandwidth in X band with linearity error less than $1.4×10^{-4}.$ It consumes only 7 mA under 1.2 V power supply. The measured phase noise is -105dBc/Hz at 1MHz offset with a centre frequency of 10 GHz.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1776
Ending Page	1779
File Size	634437
Page Count	4
File Format	PDF
e-ISBN	9781479934324
DOI	10.1109/ISCAS.2014.6865500
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Synthesizers Phase noise Voltage-controlled oscillators Frequency synthesizers Frequency measurement Bandwidth phase locked loop FMCW frequency synthesizer X band radar
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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