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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Esmaeelzadeh, H. Sharifkhani, M. Shabany, M. |
| Copyright Year | 2014 |
| Description | Author affiliation: Sch. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran (Esmaeelzadeh, H.; Sharifkhani, M.; Shabany, M.) |
| Abstract | This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW. |
| Sponsorship | IEEE Circuits Syst. Soc. |
| Starting Page | 1147 |
| Ending Page | 1150 |
| File Size | 582781 |
| Page Count | 4 |
| File Format | |
| e-ISBN | 9781479934324 |
| DOI | 10.1109/ISCAS.2014.6865343 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-06-01 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitors Noise Pipelines Power demand CMOS integrated circuits Capacitance Power dissipation |
| Content Type | Text |
| Resource Type | Article |
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