NDLI: Low-cost high-quality constant offset injection for SEIR-based ADC built-in-self-test

Content Provider	IEEE Xplore Digital Library
Author	Xiankun Jin Nan Sun
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA (Nan Sun) \|\| Freescale Discovery Labs., Freescale Semicond., Austin, TX, USA (Xiankun Jin)
Abstract	Linearity test is a fundamental test for ADCs in production. The stringent linearity requirement for an on-chip signal generator has made ADC built-in-self-test (BIST) solutions prohibitive in the past. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it still requires the addition of a highly stable voltage offset, which remains a daunting task. To solve this problem, this paper proposes a simple and low-power method to inject the required constant offset. It exploits the inherent capacitive sample-and-hold circuit used in various ADC architectures. It ensures the injected offset to have a very high constancy, which results in an accurate INL estimation. A 16-bit SAR ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	285
Ending Page	288
File Size	1661116
Page Count	4
File Format	PDF
e-ISBN	9781479934324
DOI	10.1109/ISCAS.2014.6865121
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Built-in self-test Mathematical model Linearity Estimation error System-on-chip Histograms
Content Type	Text
Resource Type	Article

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