NDLI: A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells

Content Provider	IEEE Xplore Digital Library
Author	Hong Zhu Kursun, V.
Copyright Year	2014
Description	Author affiliation: Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China (Hong Zhu; Kursun, V.)
Abstract	Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing power supply voltage in scaled CMOS technologies. Triple-threshold-voltage seven-transistor (7T), eight-transistor (8T), and nine-transistor (9T) SRAM cells are characterized for layout area, data stability, write voltage margin, idle mode leakage currents, data access speed, and active power consumption considering process parameter fluctuations in a TSMC 65 nm CMOS technology in this paper. The single-ended and differential read / write schemes are also compared for data access speed and power consumption in SRAM circuits.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	2185
Ending Page	2188
File Size	549150
Page Count	4
File Format	PDF
e-ISBN	9781479934324
DOI	10.1109/ISCAS.2014.6865602
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SRAM cells Arrays CMOS integrated circuits CMOS technology Layout Circuit stability power consumption Memory integration density noise immunity write voltage margin leakage current data access speed
Content Type	Text
Resource Type	Article

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