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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sakare, M. Gupta, S. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Electr. Eng., Indian Inst. of Technol. (IIT) - Bombay, Mumbai, India (Sakare, M.; Gupta, S.) |
| Abstract | This paper presents an inductorless full rate pseudo-random binary sequence generator (PRBSG). Data rate of the PRBSG can be enhanced by 23% using internal pre-emphasis. The technique uses D flip-flops (DFFs) as 1-tap decision feedback equalizers (DFE) to equalize the outputs of the previous DFFs. This makes every DFF a DFE circuit, which is also used as a delay element for the PRBSG. The proposed technique increases the data-rate of the PRBSG significantly with minor increase in area and power. A design methodology to find the feedback factor of pre-emphasis technique using least square estimation is also presented. Post layout simulation in standard 90 nm CMOS technology of the $2^{7}-1$ PRBSG confirms operation of the circuit at a data-rate of 13 Gb/s with peak to peak jitter of 8 ps, while consuming 222 mW off a 1 V supply, without using inductors. |
| Sponsorship | IEEE Circuits Syst. Soc. |
| Starting Page | 746 |
| Ending Page | 749 |
| File Size | 683067 |
| Page Count | 4 |
| File Format | |
| e-ISBN | 9781479934324 |
| DOI | 10.1109/ISCAS.2014.6865243 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-06-01 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Generators Decision feedback equalizers CMOS integrated circuits Layout CMOS technology Latches Least squares approximations High-speed integrated circuits Signal generators current mode logic decision feedback equalizer inductorless |
| Content Type | Text |
| Resource Type | Article |
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