NDLI: Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications

Content Provider	IEEE Xplore Digital Library
Author	Spivak, A. Yadid-Pecht, O.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada (Spivak, A.; Yadid-Pecht, O.)
Abstract	A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10 bit Analog to Digital Converter (ADC) was embedded as a step towards implementing an integrated Lab on a Chip (LoC) platform. Herein, we describe the main milestones of the chip components design along with simulated performance results obtained using 0.18um tool kit. The simulation results indicate that the proposed system achieves sub electron KTC noise, 10 bit of Effective Number of Bits (ENOB), 50dB Signal to Noise Ratio (SNR), up to 102dB Dynamic Range (DR) @ 33 frames per second. A 128 × 128 CMOS image sensor was fabricated in 0.18um process and successfully simulated.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	45
Ending Page	48
File Size	992654
Page Count	4
File Format	PDF
e-ISBN	9781479934324
DOI	10.1109/ISCAS.2014.6865061
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise CMOS integrated circuits Switches Transistors Capacitance Arrays Capacitors Sensor Active Pixel Sensor (APS) Charge Transfer CMOS Image Sensors Low Noise Low Light
Content Type	Text
Resource Type	Article

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