NDLI: A new fault injection method for evaluation of combining SEU and SET effects on circuit reliability

Content Provider	IEEE Xplore Digital Library
Author	Kejun Wu Pahlevanzadeh, H. Peng Liu Qiaoyan Yu
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of New Hampshire, Durham, NH, USA (Kejun Wu; Pahlevanzadeh, H.; Qiaoyan Yu) \|\| Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China (Peng Liu)
Abstract	We propose a new dual-level fault injection method for evaluating combination effect of single event upsets (SEUs) and single event transients (SETs). The proposed interaction method allows collaborative simulation on register-transfer level (RTL) and gate level. Conventional fault injection methods or fault model techniques typically aim at SEUs or SETs, rather than the combination of SETs and SEUs. As a logic depth and clock period decrease, SEUs and SET are likely to co-exist, which further challenges circuit reliability. To facilitate the investigation of advanced SEU and SET management methods, our fault injection method considers both SETs and SEUs. We apply the proposed method to two ITC'99 benchmark circuits to analyze the mutual masking effect between SETs and SEUs. Simulations performed on the two circuits show that SET duration time is the dominant factor affecting the mutual masking effect. If SEU duration time changes (but not beyond one cycle), the maximum masked error ratio is up to five times the minimum masked error ratio. We also observed that doubling clock frequency results in the average masked error ratio varying from 3% to 10%.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	602
Ending Page	605
File Size	729568
Page Count	4
File Format	PDF
e-ISBN	9781479934324
DOI	10.1109/ISCAS.2014.6865207
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Clocks Single event upsets Logic gates Integrated circuit modeling Integrated circuit reliability ITC'99 fault injection reliability error masking combining effect SET SEU
Content Type	Text
Resource Type	Article

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