NDLI: Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain

Content Provider	IEEE Xplore Digital Library
Author	Blaquiere, Y. Basile-Bellavance, Y. Berrima, S. Savaria, Y.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci., Microelectron. Group, Univ. du Q a Montreal, Montreal, QC, Canada (Blaquiere, Y.) \|\| Dept. of Electr. Eng., Polytech. Montreal, Montréal, QC, Canada (Basile-Bellavance, Y.; Berrima, S.; Savaria, Y.)
Abstract	In this paper, a novel technique to get a defect tolerant JTAG compliant scan chain in very large area integrated circuits (VLAIC) is presented. It was ruled that wafer-scale VLAICs require structural regularity and defect-tolerance to be cost effective. Using only one scan chain, as typically used in PCBs, would make the whole VLAIC unusable if a single defect is present in the chain. The proposed technique regularly distributes JTAG Test Access Port (TAP) controllers with test data ports linked to two or more neighbor test data ports. One TAP controller is wired as the entry point and another as the exit point of the scan chain that must be configured according to defect locations. An externally controlled wormhole like routing algorithm can be used for functional link discovery. This paper also proposes a mechanism to make defect tolerant access to test data registers, controlled from neighbor TAP controllers. Our technique has been successfully implemented and validated in a wafer-scale like integrated circuit used in a platform for electronic system prototyping. The logic area of this defect-tolerant configurable JTAG scan chain technique occupies 5% of the test logic and 0.3 % of the cell logic when links to four nearest neighbors are included.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	2559
Ending Page	2562
File Size	954924
Page Count	4
File Format	PDF
e-ISBN	9781479934324
DOI	10.1109/ISCAS.2014.6865695
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Microprocessors Registers Ports (Computers) Integrated circuit interconnections Logic gates
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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