NDLI: Radiation tolerant SPI-programmable delay line for high energy physics experiments

Content Provider	IEEE Xplore Digital Library
Author	Mauricio, J. Gascon Fora, D. Picatoste, E. Grauges, E. Garrido, L. Vilasis-Cardona, X. Machefert, F. Duarte, O. Lefrancois, J.
Copyright Year	2014
Description	Author affiliation: LIFAELS, La Salle - Univ. Ramon Llull, Barcelona, Spain (Mauricio, J.; Vilasis-Cardona, X.) \|\| DECM & ICC, Univ. de Barcelona, Barcelona, Spain (Gascon Fora, D.; Picatoste, E.; Grauges, E.; Garrido, L.) \|\| INP2P3, LAL Univ. de Paris-Sud, Orsay, France (Machefert, F.; Duarte, O.; Lefrancois, J.)
Abstract	This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) to be used in the upgrade of the data acquisition electronics of the upgrade of the LHCb calorimeters. in order to shift the phase of the clock (25 ns) in steps of 1ns, with a 55ps jitter and 21.5ps of delay line linearity. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in AMS CMOS 0.35um technology.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	770
Ending Page	773
File Size	1102405
Page Count	4
File Format	PDF
e-ISBN	9781479934324
DOI	10.1109/ISCAS.2014.6865249
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Delay lines Registers Noise Tunneling magnetoresistance MOSFET
Content Type	Text
Resource Type	Article

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