NDLI: Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations

Content Provider	IEEE Xplore Digital Library
Author	Jungseob Lee Davoodi, A.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI (Jungseob Lee)
Abstract	This paper is a case study of dual-14 configurations of an SRAM cell considering process-induced $V_{t}$ variations. Dual threshold voltage assignment is an effective technique to reduce leakage power without any area overhead, however as we will show the quality of a dual-threshold assignment highly varies due to process parameter variations in deca-nanometer designs of today. We analyze and compare the effects of process-induced $V_{t}$ variations in 11 dominant dual-14 cell configurations. Under process variations each configuration is evaluated based on the probability density functions (pdfs) of its read delay, leakage current and read stability, accurately obtained using Monte Carlo simulations for 90nm generic process design kit of Cadence. Comparison of different cell configurations is based on evaluating these pdfs at points corresponding to a desired yield. We show that the choice of the best $dual-V_{t}$ configuration varies depending on a given yield, and show tradeoff plots between read delay, leakage and read margin of different configurations under variations.
Starting Page	3018
Ending Page	3021
File Size	1759608
Page Count	4
File Format	PDF
ISBN	1424409209
DOI	10.1109/ISCAS.2007.377982
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Delay Threshold voltage Process design Probability density function Fluctuations Robustness Stability analysis Leakage current Power dissipation
Content Type	Text
Resource Type	Article

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