NDLI: A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme

Content Provider	IEEE Xplore Digital Library
Author	Saihua Lin Huazhong Yang Rong Luo
Copyright Year	2007
Description	Author affiliation: Dept. of Electron. Eng., Tsinghua Univ., Beijing (Saihua Lin; Huazhong Yang; Rong Luo)
Abstract	Power has become an important concern for nanometer circuit design as well as timing characteristic. In this paper, a novel low power interface circuit design technique was proposed for multiple voltage islands scheme by using output feedback, conditional switch, and pulsed clock technique. The method was applied to new types of flip-flops and combinational logics to eliminate level converters and remove redundant switching activities. Combined with multiple VTH technique, a low clock swing flip-flop is designed to verify our new method. Experimental results show that the leakage power of the new flip-flop can be reduced by an average of 58.14% in standby mode and the total power consumption can be reduced by an average of 55.76% in active mode, while the delay time stays the same
Starting Page	1401
Ending Page	1404
File Size	331734
Page Count	4
File Format	PDF
ISBN	1424409209
DOI	10.1109/ISCAS.2007.378490
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis Voltage Flip-flops Switches Clocks Timing Output feedback Switching circuits Pulse circuits Logic
Content Type	Text
Resource Type	Article

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